4-mbit (512k x 8) static ram cy7c1049dv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05475 rev. *c revised april 3, 2006 features ? pin- and function-compatible with cy7c1049cv33 ?high speed ?t aa = 10 ns ? low active power ?i cc = 90 ma @ 10 ns (industrial) ? low cmos standby power ?i sb2 = 10 ma ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features ? available in lead-free 36-l ead (400-mil) molded soj v36 and 44-pin tsop ii zs44 packages functional description [1] the cy7c1049dv33 is a high-performance cmos static ram organized as 512k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1049dv33 is available in standard 400-mil-wide 36-pin soj package and 44-pin tsop ii package with center power and ground (revolutionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 14 23 24 28 27 26 25 29 32 31 30 top view soj 12 13 33 36 35 34 16 15 21 22 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 5 i/o 4 a 9 a 0 i/o 0 i/o 1 i/o 2 oe a 17 a 16 a 13 ce a 9 a 18 18 17 19 20 gnd i/o 7 i/o3 i/o 6 v cc a 10 a 11 nc nc a 10 a 6 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 7 a 8 a 9 nc nc nc nc a 18 v ss nc a 15 a 0 a 3 i/o 0 a 4 ce a 17 a 12 a 1 a 2 18 17 20 19 i/o 1 27 28 25 26 22 21 23 24 nc v ss we i/o 2 i/o 3 a 5 nc a 16 v cc oe i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 13 a 11 a 10 nc nc nc selection guide -10 (industrial) -12 (automotive) [2] unit maximum access time 10 12 ns maximum operating current 90 95 ma maximum cmos standby current 10 15 ma notes: 1. for guidelines on sram system design, please refer to the ?syst em design guidelines? cypress ap plication note, available on t he internet at www.cypress.com. 2. automotive product information is preliminary. [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.3v to +4.6v dc voltage applied to outputs in high-z state [3] ....................................?0.3v to v cc + 0.3v dc input voltage [3] .................................?0.3v to v cc + 0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .... ........... .............. ......>2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc speed industrial ?40 c to +85 c3.3v 0.3v 10 ns automotive ?40 c to +125 c 3.3v 0.3v 12 ns electrical characteristics over the operating range parameter description test conditions -10 (industrial) -12 (automotive) unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih [3] input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il [3] input low voltage [3] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 100mhz 90 -ma 83mhz 80 95 ma 66mhz 70 85 ma 40mhz 60 75 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih ; v in > v ih or v in < v il , f = f max 20 25 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 15 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out i/o capacitance 8 pf thermal resistance [4] parameter description test conditions soj package tsop ii package unit ja thermal resistance (junction to ambient) [4] still air, soldered on a 3 4.5 inch, two-layer printed circuit board 57.91 50.66 c/w jc thermal resistance (junction to case) [4] 36.73 17.17 c/w notes: 3. v il (min.) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 3 of 8 ac test loads and waveforms [5] ac switching characteristics [6] over the operating range parameter description -10 (industrial) -12 (automotive) unit min. max. min. max. read cycle t power [7] v cc (typical) to the first access 100 100 s t rc read cycle time 10 12 ns t aa address to data valid 10 12 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 10 12 ns t doe oe low to data valid 5 6ns t lzoe oe low to low-z 0 0 ns t hzoe oe high to high-z [8, 9] 5 6ns t lzce ce low to low-z [9] 3 3 ns t hzce ce high to high-z [8, 9] 5 6ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 10 12 ns write cycle [10, 11] t wc write cycle time 10 12 ns t sce ce low to write end 7 8 ns t aw address set-up to write end 7 8 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 7 8 ns t sd data set-up to write end 5 6 ns t hd data hold from write end 0 0 ns t lzwe we high to low-z [9] 3 3 ns t hzwe we low to high-z [8, 9] 5 6ns notes: 5. ac characteristics (except high-z) are tested using the load conditions shown in figure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). 6. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. t power gives the minimum amount of time that the power supply should be at stable, typical v cc values until the first memory access can be performed. 8. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads. transition is measured when the outputs enter a high impedance state. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. 11. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 3.3v output 5 pf (c) r 317 ? r2 351 ? high-z characteristics: 10 ns device [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 4 of 8 data retention characteristics over the operating range parameter description conditions [13] min. max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v ind?l 10 ma auto 15 ma t cdr [4] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 [14, 15] read cycle no. 2 (oe controlled) [15, 16] notes: 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s 13. no input may exceed v cc + 0.3v. 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 5 of 8 write cycle no. 1 (we controlled, oe high during write) [17, 18] write cycle no. 2 (we controlled, oe low) [18] notes: 17. data i/o is high-impedance if oe = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 19. during this period the i/os are in the output state and input signals should not be applied. switching waveforms(continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 19 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 19 [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 6 of 8 write cycle no. 3 (ce controlled) [17, 18] switching waveforms(continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o truth table ce oe we i/o 0 ?i/o 7 mode power h x x high-z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 10 cy7c1049dv33-10vxi 51-85090 36-lead (400-mil) molded soj (pb-free) industrial cy7c1049dv33-10zsxi 51-85087 44-pin tsop ii (pb-free) 12 cy7c1049dv33-12vxe 51-85090 36-lead (400-mil) molded soj (pb-free) automotive CY7C1049DV33-12ZSXE 51-85087 44-pin tsop ii (pb-free) please contact your local cypress sales repr esentative for availability of these parts. [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams 36-lead (400-mil) molded soj (51-85090) 51-85090-*b 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy7c1049dv33 document #: 38-05475 rev. *c page 8 of 8 document history page document title: cy7c1049dv33 4-mbit (512k x 8) static ram document number: 38-05475 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance data sheet for c9 ipp *a 233729 see ecn syt 1.ac, dc parameters are modified as per eros(spec # 01-2165) 2.pb-free offering in the ?ordering information? *b 351096 see ecn pci changed from advance to preliminary removed 20 ns speed bin corrected dc voltage (min) value in maximum ratings section from - 0.5 to - 0.3v redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 100, 80 and 67 ma to 90, 80 and 75 ma for 8, 10 and 12ns speed bins respectively i cc (ind?l): changed from 80 and 67 ma to 90 and 85 ma for 10 and 12ns speed bins respectively added v ih(max ) spec in note# 2 changed reference voltage level for measurement of hi-z parameters from 500 mv to 200 mv added data retention characteristics/waveform and footnotes 11 and 12 changed package diagram name from 44 -pin tsop ii z44 to 44-pin tsop ii zs44 changed part names from z to zs in the ordering information table added 8 ns parts in the ordering information table added lead-free ordering information shaded ordering information table *c 446328 see ecn nxr converted from preliminary to final removed -8 speed bin removed commercial operating range product information added automotive operating range product information updated thermal resistance table updated footnote #8 on high-z parameter measurement replaced package name column with package diagram in the ordering information table [+] feedback [+] feedback
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